 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| (R) TDA7503 DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS PRODUCT PREVIEW Dual 24-bit 40 MIPS DSP Cores 8 bit Microcontroller 4 receive and 5 transmit stereo channels of Serial Audio Interface Synchronous Serial Interface for communication with external processor FIFO based mailboxes for inter-processor communications External Memory Interface to 128Kb SRAM or 1Mb DRAM CORDIC co-processor Programmable PLL to suite wide range of external crystal oscillation frequencies SPI control interface Powerful debug interfaces 1280 words Program Memory for DSP1, 768 words Program Memory for DSP0 256 words X and Y Data RAM and Data ROM for each DSP 256 byte Data RAM for Microcontroller 768 byte Auxiliary RAM for Microcontroller BLOCK DIAGRAM TQFP100 DESCRIPTION The device is a high-performance Digital Signal Processing IC particularly suited to Audio applications. The device contains two 24-bit 40 MIPS DSP cores delivering a total of 80 MIPS of DSP processing power. There is also an embedded 8bit Microcontroller to handle all control functions. All data and program memories for both DSP cores are on-chip. A variety of highly programmable and flexible peripheral blocks for both the Microcontroller and the DSPs have been integrated to form a powerful audio processing system on a single chip. Serial Audio Interface Host Interface 0 Host Interface 1 Synchronous Audio Interface XDB0 XAB0 XDB1 XAB1 SRAM/ D RAM Interface XCHG Interface C ordic Ari thmetic U nit M8051 CORE Control Interface AUX-RAM 768 Bytes Y-RAM0 Y-ROM0 PAB0 YDB0 PDB0 YAB0 XDB0 XAB0 YDB1 YAB1 PDB1 PAB1 XDB1 XAB1 Serial Peripheral Interface AUX-RAM 256 Bytes Mi cro Memory Interface Watchdog Timer PLL Clock Oscillator MCLK DCLK Y-RAM1 Y-ROM1 X-RAM0 X-ROM0 X-RAM1 X-ROM1 P-RAM0 P-ROM0 P-RAM1 P-ROM1 DSP0 CORE DSP1 CORE DEBUG Interface July 1999 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/26 TDA7503 ABSOLUTE MAXIMUM RATINGS Symbol VDDC V DDP VI, VIN Top Tstg Core DC Supply voltage Pads DC Supply voltage Digital or analog input voltage Operative temperature range Storage temperature range (plastic) Parameter Value -0.5 to 5 -0.5 to 6.5 -0.5 to (VDDP +0.5) -40 to 85 -55 to 150 Unit V V V C C PIN CONNECTION GPIO6(P1.6) GPIO5(P1.5) GPIO4(P1.4) GPIO3(P1.3) GPIO2(P1.2) GPIO1(P1.1) GPIO0(P1.0) VDDE5_MI2 VSSE5_MI2 RAD0(P0.0) RAD1(P0.1) RAD2(P0.2) RAD3(P0.3) RAD4(P0.4) RAD5(P0.5) RAD6(P0.6) RAD7(P0.7) 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 INT0(P3.2) INT1(P3.3) RXD(P3.0) TXD(P3.1) T0(P3.4) WR(P3.6) 85 RD(P3.7) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 xALE 84 83 82 81 80 79 78 77 T1(P3.5) VDDI3_CORE3 VSSI3_CORE3 RESET MISO MOSI SCLK SS/GPIOS VSSE5_CI1 VDDE5_CI1 LRCKR SCLKR SDI3 SDI2 SDI1 SDI0 SDO4 SDO3 SDO2 SDO1 SDO0 VSSI3_CORE2 VDDI3_CORE2 SCLKT LRCKT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RA10(P2.2) VSSI3_CORE4 VDDI3_CORE4 VSSE5_MI1 VDDE5_MI1 XPSEN RA11(P2.3) RA9(P2.1) RA8(P2.0) RA13(P2.5) RA14(P2.6) RA15(P2.7) RA12(P2.4) SRA10/DRA6 DRD SRA11/DRA7 SRA9/DRA5 VDDE5_DR2 VSSE5_DR2 SRA8/DRA4 SRA13/RAS VSSI3_CORE1 VDDI3_CORE1 DWR ALE/CAS DBCK/OS1 DBIN/OS0 XTO FILT SRA_D7/DRA3 SRA_D6/DRA2 SRA_D5/DRA1 SRA_D4/DRA0 SRA_D3/DRD3 SRA_D2/DRD2 SRA_D1/DRD1 SRA_D0/DRD0 SRA12/DRA8 VDDE5_SA1 VDDE5_DR1 VSSE5_DR1 PVCC SCANEN DBOUT XTI PGND TESTEN VSSE5_SA1 DBRQN DBSEL D97AU693 THERMAL DATA Symbol Rth j-amb Parameter Thermal resistance Junction to Ambient Value 85 Unit C/W 2/26 TDA7503 PIN DESCRIPTION N. 11 Name LRCKR Type I Reset Status (1) - Function Audio Serial Port Receive Left/Right Frame Sync. The Left/Right select signal for received serial audio data. This signal has a frequency equal to the audio sample rate. Audio Serial Port Receive Bit Clock. SCLK clocks received digital audio data into pins SDI0, SDI1, SDI2, and SDI3 Stereo Digital Audio Data. SDI0 is a stereo digital audio data input pin channel 0. Stereo Digital Audio Data. SDI1 is a stereo digital audio data input pin channel 1. Stereo Digital Audio Data. SDI2 is a stereo digital audio data input pin channel 2. Stereo Digital Audio Data / Serial Receive Data. SDI3 is a stereo digital audio data input pin and is multiplexed with the SSI's Serial Receive Data Input channel 3. Audio Serial Port Transmit Left/Right Frame Sync /Frame Sync. The Left/Right select signal for transmitted serial audio data. This signal has a frequency equal to the audio sample rate. This signal is multiplexed with the SSI's Frame Sync Input. Audio Serial Port Transmit Bit Clock/SSI Serial Bit Clock. SCLK clocks digital audio data out of pins SDO0, SDO1, SD02, SD03, and SD04. This pin is multiplexed with the SSI's serial bit clock. Stereo Digital Audio Data. SDO0 is a stereo digital audio data output pin channel 0. Stereo Digital Audio Data. SDO1 is a stereo digital audio data output pin channel 1. Stereo Digital Audio Data. SDO2 is a stereo digital audio data output pin channel 2. Stereo Digital Audio Data. SDO3 is a stereo digital audio data output pin channel 3. Stereo Digital Audio Data /Serial Transmit Data. SDO4 is a stereo digital audio data output pin and is multiplexed with the SSI's Serial Transmit Data Output channel 4. SCAN Enable. Enable SCAN Path and MUXing of SCANIN and SCANOUT Pins. Test Enable. Enable Scan Mode Clocks. An active low signal will enable the same clock to all scan chains. This pin also makes all latches transparent. DSP SRAM Multiplexed Address/Data Line 0/DSP DRAM Data Line 0.When in SRAM Mode these pins act as the EMI multiplexed address and data line 0. When in DRAM Mode they act as the EMI data line 0. DSP SRAM Multiplexed Address/Data Line 1/DSP DRAM Data Line 1.When in SRAM Mode these pins act as the EMI multiplexed address and data line 1. When in DRAM Mode they act as the EMI data line 1. DSP SRAM Multiplexed Address/Data Line 2/DSP DRAM Data Line 2.When in SRAM Mode these pins act as the EMI multiplexed address and data line 2. When in DRAM Mode they act as the EMI data line 2. DSP SRAM Multiplexed Address/Data Line 3/DSP DRAM Data Line 3.When in SRAM Mode these pins act as the EMI multiplexed address and data line 3. When in DRAM Mode they act as the EMI data line 3. DSP SRAM Multiplexed Address/Data Line 4/DSP DRAM Address Line 0. When in SRAM Mode these pins act as the EMI multiplexed address and data line 4. When in DRAM Mode they act as the EMI address line 0. 12 16 15 14 13 SCLKR SDI0 SDI1 SDI2 SDI3 I I I I I - - - - - 25 LRCKT I - 24 SCLKT I - 21 20 19 18 17 SDO0 SDO1 SDO2 SDO3 SDO4 O O O O O High High High High High 34 33 SCANEN TESTEN I I - - 49 SRA_D0/DRD0 I/O I 48 SRA_D1/DRD1 I/O I 47 SRA_D2/DRD2 I/O I 46 SRA_D3/DRD3 I/O I 43 SRA_D4/DRA0 I/O O, High 3/26 TDA7503 PIN DESCRIPTION (continued) N. 42 Name SRA_D5/DRA1 Type I/O Reset Function Status (1) O, High DSP SRAM Multiplexed Address/Data Line 5/DSP DRAM Address Line 1. When in SRAM Mode these pins act as the EMI multiplexed address and data line 5. When in DRAM Mode they act as the EMI address line 1. O, High DSP SRAM Multiplexed Address/Data Line 6/DSP DRAM Address Line 2. When in SRAM Mode these pins act as the EMI multiplexed address and data line 6. When in DRAM Mode they act as the EMI address line 2. O, High DSP SRAM Multiplexed Address/Data Line 7/DSP DRAM Address Line 3. When in SRAM Mode these pins act as the EMI multiplexed address and data line 7. When in DRAM Mode they act as the EMI address line 3. DSP SRAM Address Line 8/DSP DRAM Address Line 4. When in SRAM Mode these pins act as the EMI address line 8. When in DRAM Mode they act as the EMI address line 4. DSP SRAM Address Line 9/DSP DRAM Address Line 5. When in SRAM Mode these pins act as the EMI address line 9. When in DRAM Mode they act as the EMI address line 5. DSP SRAM Address Line 10/DSP DRAM Address Line 6. When in SRAM Mode these pins act as the EMI address line 10.When in DRAM Mode they act as the EMI address line 6. DSP SRAM Address Line 11/DSP DRAM Address Line 7. When in SRAM Mode these pins act as the EMI address line 11. When in DRAM Mode they act as the EMI address line 7. DSP SRAM Address Line 12/DSP DRAM Address Line 8. When in SRAM Mode these pins act as the EMI address line 12. When in DRAM Mode they act as the EMI address line 8. DSP SRAM Address Line 13/DRAM Row Address Strobe. When in SRAM Mode this pin acts as the EMI address lines 13. When in DRAM Mode this pin acts as the row address strobe. DSP SRAM Address latch enable/colomn Address. When in SRAM Mode this pin acts as the EMI Address Latch Enable. When in DRAM Mode this pin acts as the column address strobe. DSP SRAM Write Enable/DRAM Write Enable. This pin serves as the write enable for the EMI when in DRAM and SRAM Modes. DSP SRAM Read Enable/DRAM Read Enable. This pin serves as the read enable for the EMI when in DRAM and SRAM Modes. Debug Port Bit Clock/Chip Status 1. The serial clock for the Debug Port is provided when an input. When an output, together with OS0 provides information about the chip status. Can also be used as GPIO for the 8051. Debug Port Serial Input/Chip Status 0. The serial data input for the Debug Port is provided when an input. When an output, together with OS1 provides information about the chip status. Can also be used as GPIO for the 8051. Debug Port Serial Output. The serial data output for the Debug Port. Can also be used as a GPIO for the 8051. Debug Port Request Input. Means of entering the Debug mode of operation. Debug Port MUX Selection. Selects either DSP0 or DSP1 to be connected to the Debug Port pins. Microcontroller High Byte Address Lines. This pin is the address line 8 of a 16 bit address, for external EPROM and memory mapped devices. It can also act as GPIO using the P2 and P2DIR registers. Microcontroller High Byte Address Lines. This pin is the address line 9 of a 16 bit address, for external EPROM and memory mapped devices. It can also act as GPIO using the P2 and P2DIR registers. 41 SRA_D6/DRA2 I/O 40 SRA_D7/DRA3 I/O 56 SRA8/DRA4 O High 59 SRA9/DRA5 O High 62 SRA10/DRA6 O High 60 SRA11/DRA7 O High 50 SRA12/DRA8 O High 55 SRA13/RAS O High 51 ALE/CAS O High 52 61 36 DWR DRD DBCK/OS1 O O I/O High High I 37 DBIN/OS0 I/O I 35 38 39 67 DBOUT DBRQN DBSEL RA8(P2.0) I/O I I I/O I - - I 68 RA9(P2.1) I/O I 4/26 TDA7503 PIN DESCRIPTION (continued) N. 75 Name RA10(P2.2) Type I/O Reset Function Status (1) I Microcontroller High Byte Address Lines. This pin is the address line 10 of a 16 bit address, for external EPROM and memory mapped devices. It can also act as GPIO using the P2 and P2DIR registers. I Microcontroller High Byte Address Lines. This pin is the address line 11 of a 16 bit address, for external EPROM and memory mapped devices. It can also act as GPIO using the P2 and P2DIR registers. I Microcontroller High Byte Address Lines. This pin is the address line 12 of a 16 bit address, for external EPROM and memory mapped devices. It can also act as GPIO using the P2 and P2DIR registers. Microcontroller High Byte Address Lines. This pin is the address line 13 of a 16 bit address, for external EPROM and memory mapped devices. It can also act as GPIO using the P2 and P2DIR registers. Microcontroller High Byte Address Lines. This pin is the address line 14 of a 16 bit address, for external EPROM and memory mapped devices. It can also act as GPIO using the P2 and P2DIR registers. Microcontroller High Byte Address Lines. This pin is the address line 15 of a 16 bit address, for external EPROM and memory mapped devices. It can also act as GPIO using the P2 and P2DIR registers. Microcontroller Address/Data Pins. This pin is the multiplexed address and data line bit 0 for external EPROM and memory mapped peripherals. It can also act as GPIO using the P0 and P0DIR registers. Microcontroller Address/Data Pins. This pin is the multiplexed address and data line bit 1 for external EPROM and memory mapped peripherals. It can also act as GPIO using the P0 and P0DIR registers. Microcontroller Address/Data Pins. This pin is the multiplexed address and data line bit 2 for external EPROM and memory mapped peripherals. It can also act as GPIO using the P0 and P0DIR registers. Microcontroller Address/Data Pins. This pin is the multiplexed address and data line bit 3 for external EPROM and memory mapped peripherals. It can also act as GPIO using the P0 and P0DIR registers. Microcontroller Address/Data Pins. This pin is the multiplexed address and data line bit 4 for external EPROM and memory mapped peripherals. It can also act as GPIO using the P0 and P0DIR registers. Microcontroller Address/Data Pins. This pin is the multiplexed address and data line bit 5 for external EPROM and memory mapped peripherals. It can also act as GPIO using the P0 and P0DIR registers. Microcontroller Address/Data Pins. This pin is the multiplexed address and data line bit 6 for external EPROM and memory mapped peripherals. It can also act as GPIO using the P0 and P0DIR registers. Microcontroller Address/Data Pins. This pin is the multiplexed address and data line bit 7 for external EPROM and memory mapped peripherals. It can also act as GPIO using the P0 and P0DIR registers. Microcontroller External Address Latch Enable. This pin is the address latch enable. A logic high indicates that address/data lines 7 through 0 represent an address. Inactive for Program/Data fetches from internal AUX. Microcontroller Write Strobe. External data memory write strobe. This pin can also act as GPIO using the P3 and P3DIR registers. Microcontroller Read Strobe. External data memory read strobe. Active Low, or GPIO. This pin can also act as GPIO using the P3 and P3DIR registers. Disabled by setting the RDSEL bit in the PINCTL register. Microcontroller External Program Memory Enable. External program memory enable pin. Active Low. Changes functionality to RD when Microcontroller is fetching instructions out of internal AUX ram. Controlled by the PSSEL and PSBIT bits in the PINCTL register. 69 RA11(P2.3) I/O 63 RA12(P2.4) I/O 66 RA13(P2.5) I/O I 65 RA14(P2.6) I/O I 64 RA15(P2.7) I/O I 83 RAD0(P0.0) I/O I 82 RAD1(P0.1) I/O I 81 RAD2(P0.2) I/O I 80 RAD3(P0.3) I/O I 79 RAD4(P0.4) I/O I 78 RAD5(P0.5) I/O I 77 RAD6(P0.6) I/O I 76 RAD7(P0.7) I/O I 84 xALE I/O I 85 86 WR(P3.6) RD(P3.7) I/O I/O I I 70 XPSEN I/O I 5/26 TDA7503 PIN DESCRIPTION (continued) N. 4 Name RESET Type I/O Reset Function Status (1) I System Reset. A logic low level applied to RESET input initializes the microcontroller. The micro is responsible for initializing the DSPs. If the watchdog timer overflow occurs this pin is driven low for 1 watchdog timer cycle. During Debug Mode if this pin is pulled low in while the DBRQN line is pulled low then the DSP pointed to by the DBSEL pin will be reset. I I Microcontroller Standard Serial Interface (Asynchronous) Input Data. Or GPIO. This pin can also act as GPIO using the P3 and P3DIR registers. Microcontroller Standard Serial Interface (Asynchronous) Output Data. Or GPIO. This pin can also act as GPIO using the P3 and P3DIR registers. Microcontroller Interrupt 0. When pulled low, INT0 asserts a microcontroller external interrupt. In addition, if this pin is pulled low during powerdown this allows the M8051 to resume executing intructions where it left off. This pin can also act as GPIO using the P3 and P3DIR registers. Microcontroller Interrupt 1. When pulled low, INT1 asserts a microcontroller external interrupt. In addition, if this pin is pulled low during powerdown this allows the M8051 to resume executing intructions where it left off. This pin can also act as GPIO using the P3 and P3DIR registers. Microcontroller Timer 0 External Input. Input event clock for timer 0, or GPIO. This pin can also act as GPIO using the P3 and P3DIR registers. Microcontroller Timer 1 External Input. Input event clock for timer 1, or GPIO. This pin can also act as GPIO using the P3 and P3DIR registers. Microcontroller General Purpose. This GPIO line can be configured to be digital input or output by writing to the P1 and P1DIR registers.This pin is tri-stated while the RESET pin is held low and is pulled low when RESET is released. This pin will be pulled high when in IDLE or PWRDN modes. Microcontroller General Purpose. This GPIO line can be configured to be digital input or output by writing to the P1 and P1DIR registers. At reset it is configured as an input with the output tri-stated. Microcontroller General Purpose. This GPIO line can be configured to be digital input or output by writing to the P1 and P1DIR registers. At reset it is configured as an input with the output tri-stated. Microcontroller General Purpose. This GPIO line can be configured to be digital input or output by writing to the P1 and P1DIR registers. At reset it is configured as an input with the output tri-stated. Microcontroller General Purpose. This GPIO line can be configured to be digital input or output by writing to the P1 and P1DIR registers. At reset it is configured as an input with the output tri-stated. Microcontroller General Purpose. This GPIO line can be configured to be digital input or output by writing to the P1 and P1DIR registers. At reset it is configured as an input with the output tri-stated. Microcontroller General Purpose. This GPIO line can be configured to be digital input or output by writing to the P1 and P1DIR registers. At reset it is configured as an input with the output tri-stated. Microcontroller General Purpose. Each of the six GPIO lines can be individually configured to be digital input or output by writing to the P1 and P1DIR registers. All GPIOs are configured to be inputs with the outputs tri-stated except for P1.0. This pin is tri-stated during while the RESET pin is held low and is pulled low when RESET is released. This pin will be pulled high when in IDLE or PWRDN modes. Microcontroller SPI Master Output Slave Input Serial Data . Serial Data Output for SPI type serial port when in SPI Master Mode and Serial Data Input when in SPI Slave Mode. 96 97 RXD(P3.0) TXD(P3.1) I/O I/O 99 INT0(P3.2) I/O I 98 INT1(P3.3) I/O I 100 1 87 T0(P3.4) T1(P3.5) GPIO0(P1.0) I/O I/O I/O I I I 88 GPIO1(P1.1) I/O I 89 GPIO2(P1.2) I/O I 92 GPIO3(P1.3) I/O I 93 GPIO4(P1.4) I/O I 94 GPIO5(P1.5) I/O I 95 GPIO6(P1.6) I/O I 7 SCLK I/O I 6 MOSI I/O I 6/26 TDA7503 PIN DESCRIPTION (continued) N. 5 Name MISO Type I/O Reset Function Status (1) I Microcontroller SPI Master Input Slave Output Serial Data . Serial Data Input for SPI style serial port when in SPI Master Mode and Serial Data Output when in SPI Slave Mode. I Microcontroller SPI Slave Select . Slave Select Input for SPI type serial port. This pin can be used as a GPIO when the SPI is disabled or in master mode. - High - High - - - - - - - - - - - - - - - - - - - - - PLL Clock Power Supply . Vdd Pin for PLL Clock Oscillator. Crystal Oscillator Output. Crystal Oscillator output drive. Crystal Oscillator Input. External Clock Input or crystal connection. PLL Loop Filter Capacitor Output. Capacitor connected between FILT and XGND establishes primary PLL. PLL Clock Ground Input. Ground connection for oscillator circuit. 3.3V core supply. 3.3V core supply. 3.3V core supply. 3.3V core supply. Core ground. Core ground. Core ground. Core ground. 5V supply for SAI pads. Ground for SAI pads. 5V supply for Control Interface Pads. Ground for Control Interface Pads. 5V supply for Micro Memory Interface Pads. 5V supply for Micro Memory Interface Pads. Ground for Micro Memory Interface Pads. Ground for Micro Memory Interface Pads. 5V supply for DSP EMI Interface Pads. 5V supply for DSP EMI Interface Pads. Ground for DSP EMI Interface Pads. Ground for DSP EMI Interface Pads. 8 SS/GPIOS I/O 32 28 29 30 31 53 23 2 73 54 22 3 74 27 26 10 9 71 91 72 90 44 58 45 57 PVCC XTO XTI FILT PGND VDDI3_CORE1 VDDI3_CORE2 VDDI3_CORE3 VDDI3_CORE4 VSSI3_CORE1 VSSI3_CORE2 VSSI3_CORE3 VSSI3_CORE4 VDDE5_SA1 VSSE5_SA1 VDDE5_CI1 VSSE5_CI1 VDDE5_MI1 VDDE5_MI2 VSSE5_MI1 VSSE5_MI2 VDDE5_DR1 VDDE5_DR2 VSSE5_DR1 VSSE5_DR2 I O I O I PWR PWR PWR PWR GND GND GND GND PWR GND PWR GND PWR PWR GND GND PWR PWR GND GND 7/26 TDA7503 RECOMMENDED DC OPERATING CONDITIONS Symbol VDDC VDDP Tj Parameter 3.3V Power Supply Voltage 5V Power Supply Voltage Operating Junction Temperature Test Condition Min. 3 4.5 -40 Typ. 3.3 5 Max. 3.6 5.5 125 Unit V V C GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Iil Iih Ioz C in Ilatchup Vesd Parameter Low Level Input Current Without pull-up device High Level Input Current Without pull-down device Tri-state Output leakage Without pullup/down device Input capacitance I/O Latch-up Current Electrostatic Protection V < 0V, V > V DDP Leakage < 1A 200 2000 Test Condition Vi = 0V Vi = VDDP Vo = 0V or VDDP Min. Typ. Max. 1 1 1 10 Unit A A A pF mA V 3 Note 1 1 1 2 Note 1: The leakage currents are generally very small, < 1nA. The value given here, 1mA, is a maximum that can occur after an Electrostatic Stress on the pin. Note 2: Guaranteed by design. Note 3: Human Body Model. DC ELECTRICAL CHARACTERISTICS Symbol V il Vih Vol V oh Parameter Low Level Input Voltage High Level Input Voltage Low Level Output Voltage High Level Output Voltage Iol = 2mA Iol = -2mA VDDP-0.4 0.7VDDP 0.4 Test Condition Min. Typ. Max. 0.25 VDDP Unit V V V V 1 1 Note Note 1: Takes into account 200mV voltage drop in both supply lines. 8/26 TDA7503 POWER CONSUMPTION Symbol Ptot Parameter Maximum current for core power supply @ 3.3V Value 320 Unit mA Note: 40MHz internal DSP clock at Tamb EXTERNAL CLOCKS (XTI Pin) The TDA7503 system clock is externally supplied via the XTI pin. Timings shown in this document are valid for clock rise and fall times of 3ns maximum. Symbol Fext Characteristics Max. Frequency @ XTI when PLL is disabled Value 20 Unit MHz When PLL is enabled see constraints for Internal Clocks. INTERNAL CLOCKS Symbol fDSP_MAX fP_MAX fDSP fP Icyc_DSP Icyc_P Note Note Note Note Characteristics Maximum DSP Internal Operation Frequency (dclk) Maximum P (8051) Internal Operation Frequency (mclk) Internal DSP Clock Cycle Frequency (dclk) Inernal P (8051) Clock Cycle Frequency (mclk) DSP Machine Cycle Time P (8051) Machine Cycle Time Expression 40MHz 20MHz MF Fext 2 DF MF Fext 4 DF dclk mclk/12 1: If the DCKSRC bit of the clock control register is 0 then dclk = Fext/2. 2: If the MCKSRC bit of the clock control register is 1 then mclk = Fext else of MCKSRC0 is 0 then MCLK = Fext/4. 3: DF is PLL input devide factor, bits IDF [4:0] of PLL control register one. 4: MF is PLL multiply devide factor, bits MP [6:0] of PLL control register zero. PHASE LOCKED LOOP (PLL) CHARACTERISTICS Characteristics VCO frequency when PLL enabled Recommended PLL external capacitor (pin FILT) Expression MF Fext DF Value 40 to 80 3.3 Unit MHz nF RESET Characteristics Minimum RESET assertion Expression 100/Fext Unit ns 9/26 TDA7503 SAI/SSI INTERFACE Figure 1. SAI and SSI Timings SDI0-3 Valid LRCKR Valid t lrh SCKR (RCKP=0) t sckpl tlrs tsdih t sckph tdt tsdis t sckr Timing tsckr tdt tlrs tlrh tsdid tsdih tsckph tsckpl Minimum Clock Cycle Description SCKR active edge to data out valid LRCK setup time LRCK hold time SDI setup time SDI hold time Minimum SCK high time Minimum SCK low time Value 3TDSP+5 40 5 5 5 5 0.35 tsckr 0.35 tsckr Unit ns ns ns ns ns ns ns ns Note TDSP = dsp master clock cycle time = 1/FDSP Figure 2. SAI Interrupt protocol LRCKT Left Right Left Right TDE Internal Flag set when left data written to all enabled transmitters. If this internal flag is set then right data must written to data registers before the next falling edge of LRCKT. TDE cleared when right data written to all enabled transmitters. LRCKR Left Right Left Right RDR RDR cleared when right data read from all enabled transmitters. Internal Flag set when left data read from all enabled receivers. If this internal flag is set then right data must read from data registers before the next rising edge of LRCKR. 10/26 TDA7503 Figure 3. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0. LEFT RIGHT LRCKR SCKR LSB(n-1) SDI0 MSB(word n) MSB-1 (n) MSB-2 (n) Figure 4. SAI protocol when RLRS=1; RREL=0; RCKP=1; RDIR=1. LEFT LRCKR RIGHT SCKR SDI0 MSB(n-1) LSB(word n) LSB+1 (n) LSB+2 (n) Figure 5. SAI protocol when RLRS=0; RREL=0; RCKP=0; RDIR=0. LRCKR LEFT RIGHT SCKR SDI0 LSB(n-1) MSB(word n) MSB-1 (n) MSB-2 (n) Figure 6. SAI protocol when RLRS=0; RREL=1; RCKP=1; RDIR=0. LEFT LRCKR RIGHT SCKR SDI0 LSB(n-1) MSB(word n) MSB-1 (n) MSB-2 (n) 11/26 TDA7503 Figure 7. SSI Protocol. NETWORK MODE Five Word Packet Frame Sync 0 Frame Sync 1 Data In SCK Receive Interrupts Data Word NORMAL MODE Frame Sync 0 Frame Sync 1 Data In SCK Receive Interrupts The timing diagrams for the SSI Interface are shown in Figure 7 for both Network and Normal modes. In Normal Mode the rising edge FSYNC starts the internal bit counter to allow data to be clocked in or out. When bit count is equal to the programmed word length the counter is reset and the shift register is broadside loaded into the data register. Additional SCK pulses are ignored after the counter is reset. The next word is clocked in or out starting with the next rising edge of FSYNC. 12/26 In Network Mode the rising edge FSYNC starts the internal bit counter to allow data to be clocked in or out. When bit count is equal to the programmed word length the counter is reset and the shift register is broadside loaded into the data register. At this point the FSRSD bit is set indicating that a frame sync was received with that word. After being reset the counter continues counting, clocking in the next word. Only when the next rising edge of FSYNC is detected is the packet considered complete. TDA7503 SPI INTERFACE Symbol Description MASTER tsclk tdtr tdts tsclk tdtr tdts tsckph tsckpl Clock Cycle Sclk edge to MOSI valid MISO setup time SLAVE Clock Cycle Sclk edge to MOSI valid MISO setup time Minimum SCK high time Minimum SCK low time mclk/6 40 5 mclk/12 mclk/12 s s s s s mclk/12 40 5 s s s Min Value Unit Figure 8. SPI Clocking scheme. SS SCLK (CPOL=0, CPHA=0) SCLK (CPOL=0, CPHA=1) SCLK (CPOL=1, CPHA=0) SCLK MISO/ MOSI (CPOL=1, CPHA=1) MSB 6 5 4 3 2 1 LSB Internal Strobe for Data Capture 13/26 TDA7503 MICRO MEMORY INTERFACE Figure 9. Timing diagram for External Memory Interface For the calculation of slowest access time allowed for a memory attached to the M8051, the following diagram illustrates the timing constraints. Slowest access time allowed, tacc = 4*mclk - tad - t ds, where the worst case address delay, tad = 30 ns, and the worst case data setup time, tds = 20 ns. mclk XALE XPSEN OPLOAD Address Data t ad t acc t ds GENERAL PURPOSE I/O (GPIO) INTERFACE Timing tgod tgoh tgis tgih Characteristics XTI Edge to GPIO Out Valid (GPIO Out Delay Time) XTI Edge to GPIO Out Not Valid (GPIO Out Hold Time) GPIO In Valid to XTI Edge (GPIO In Set-up Time) XTI Edge to GPIO In Not Valid (GPIO In Hold Time) mclk = 20MHz Min. -2 10 6 Max. 26 ---Unit ns ns ns ns Figure 10. GPIO Timing 14/26 TDA7503 Debug Port Interface No. 1 2 3 4 5 6 7 8 9 10 DBCK rise time DBCK fall time DBCK Low DBCK High DBCK Cycle Time DBRQN Asserted to DBOUT (ACK) Asserted DBCK High to DBOUT Valid DBCK High to DBOUT Invalid DBIN Valid to DBCK Low (Set-up) DBCK Low to DBIN Invalid (Hold) DBOUT (ACK) Asserted to First DBCK High DBOUT (ACK) Assertion Width 11 12 Last DBCK Low of Read Register to First DBCK High of Next Command Last DBCK Low to DBOUT Invalid (Hold) DBSEL setup to DBCK Characteristics dclk = 40MHz Min. --40 40 200 5 TDSP -3 15 3 2 Tc 4.5 TDSP - 3 7 TDSP + 10 3 TDSP Max. 3 3 ----42 ----5 TDSP + 7 --Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15/26 TDA7503 Figure 11. Debug Port Serial Clock Timing. Figure 12. Debug Port Acknowledge Timing. Figure 13. Debug Port Data I/O to Status Timing. Figure 14. Debug Port Read Timing. Figure 15. Debug Port DBCK Next Command After Read Register Timing. 16/26 TDA7503 EXTERNAL MEMORY INTERFACE (EMI) DRAM MODE Characteristics Page Mode Cycle Time RAS or RD Assertion to Data Valid CAS Assertion to Data Valid Column Address Valid to Data Valid CAS Assertion to Data Active RAS Assertion Pulse Width (Note 1) (Page Mode Access Only) RAS Assertion Pulse Width (Single Access Only) RAS or CAS Negation to RAS Assertion CAS Assertion Pulse Width Last CAS Assertion to RAS Negation (Page Mode Access Only) Note: 1. n is the number of successive accesses. n = 2, 3, 4, or 6. Timing Mode slow fast slow fast slow fast slow fast slow fast slow fast slow fast slow fast slow fast 40MHz Min. Max. 100 -75 --159 -109 -65 -40 -80 -55 0 -264 -189 164 114 120 70 65 40 60 35 ---------- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DRAM Refresh Timing Characteristics RAS Negation to RAS Assertion CAS Negation to CAS Assertion Refresh Cycle Time RAS Assertion Pulse Width RAS Negation to RAS Assertion for Refresh Cycle (Note 1) CAS Assertion to RAS Assertion on Refresh Cycle RAS Assertion to CAS Negation on Refresh Cycle RAS Negation to CAS Assertion on a Refresh Cycle CAS Negation to Data Not Valid Note: 1. Happens when a Refresh Cycle is followed by an Access Cycle. Timing Mode slow fast slow fast slow fast slow fast slow fast slow fast slow fast 40MHz Min. 143 93 118 68 325 225 166 116 120 70 18 160 110 114 64 0 Max. ----------------- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 17/26 TDA7503 EXTERNAL MEMORY INTERFACE (EMI) SRAM MODE Characteristics Address Valid and CS Assertion Pulse Width Address Valid to RD or WR Assertion RD or WR Assertion Pulse Width RD or WR Negation to RD or WR Assertion RD or WR Negation to Address not Valid Address Valid to Input Data Valid RD Assertion to Input Data Valid RD Negation to Data Not Valid (Data Hold Time) Address Valid to WR Negation Data Setup Time to WR Negation Data Hold Time from WR Negation WR Assertion to Data Valid WR Negation to Data High-Z (Note 1) WR Assertion to Data Active 89 23 45 39 5 --0 73 32 5 --5 40MHz Min. Max. -----72 35 ----18 23 -ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit 18/26 TDA7503 Figure 16. External Memory Interface SRAM Read Cycle. SRA_D [7:0] SRA_D [13:8] add. [7:0] data add. [13:8] ALE DRD Figure 17. External Memory Interface SRAM Write Cycle. SRA [7:0] SRA [13:8] add. [13:8] add. [7:0] data ALE DWR Figure 18. DRAM Read Cycle. DRA [8:0] Column address 2 Row address 2 Row address 1 Column address 1 RAS CAS DRD nibble 1 DRD [3:0] nibble 2 19/26 TDA7503 Figure 19. DRAM Write Cycle. Row address 1 Column address 1 Column address 2 Row address 2 DRA [8:0] RAS CAS DWR nibble 1 DRD[3:0] nibble 2 FUNCTIONAL DESCRIPTION. The Aladdin IC broken up into two distinct blocks. One block contains the two DSP Cores and their associated peripherals. The other contains the M8051 Core and its associated peripherals. The interface between the two blocks is the Host Interface. 24-BIT DSP CORE. The two DSP cores are used to process the converted analog audio data coming from the CODEC chip via the SAI and return it for analog conversion. Functions such as volume, tone, balance, and fader control, as well as spatial enhancement and general purpose signal processing may be performed by the DSPs. Some capabilities of the DSPs are listed below: Single cycle multiply and accumulate with convergent rounding and condition code generation 2 x 56-bit Accumulators Double precision multiply Scaling and saturation arithmetic 48-bit or 2 x 24-bit parallel moves 64 interrupt vector locations Fast or long interrupts possible Programmable interrupt priorities and masking 8 each of Address Registers, Address Offset Registers and Address Modulo Registers Linear, Reverse Carry, Multiple Buffer Modulo, Multiple Wrap-around Modulo address arithmetic Post-increment or decrement by 1 or by offset, Index by offset, predecrement address 20/26 Repeat instruction and zero overhead DO loops Hardware stack capable of nesting combinations of 7 DO loops or 15 interrupts/subroutines Bit manipulation instructions possible on all registers and memory locations. Also Jump on bit test. 4 pin serial debug interface Debug ccess to all internal registers, buses and memory locations 5 word deep program address history FIFO Hardware and software breakpoints for both program and data memory accesses Debug Single stepping, Instruction injection and Disassembly of program memory DSP PERIPHERALS There are a number of peripherals that are tightly coupled to the two DSP Cores. Except for the memories and the Host Interface, a single peripheral is multiplexed to both of the DSP Cores. In the case of the Host Interface(HI), for DSP to Micro communication, there are two identical peripheral blocks providing the same function to both DSP Cores. Each of the peripherals are listed below and described in the following sections. 256 x 24-Bit X-RAM. 256 x 24-Bit Y-RAM. 768 x 24-Bit Program RAM (1280 x 24 for DSP1) 256 x 24-Bit Data X-ROM. 256 x 24-Bit Data Y-ROM. TDA7503 64 x 24-Bit Boot ROM. Serial Audio Interface (SAI) multiplexed to both DSPs. Synchronous Serial Interface (SSI) multiplexed to both DSPs. XCHG Interface for DSP to DSP communication. Host Interface (HI) for DSP to Micro communication. External Memory Interface (DRAM/SRAM) multiplexed to both DSPs for time-delay. Single Debug Port multiplexed to both DSPs. Cordic Arithmetic Unit DATA AND PROGRAM MEMORY Both DSP0 and DSP1 have an identical set of Data and Program memories attached them. Each of the memories are described below and it is implied that there are two of each type, one set connected to DSP0 and the other to DSP1. The only exception is the case of the P-RAM where DSP0 has a 768 x 24-Bit PRAM and DSP1 has a 1280 x 24-Bit PRAM. 256 x 24-Bit X-RAM (XRAM) This is a 256 x 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit XRAM address, XABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit XRAM Data, XDBx(23:0), may be written to and read from the Data ALU of the DSP core. The XDBx Bus is also connected to the Internal Bus Switch so that it can be routed to and from all peripheral blocks. 256 x 24 Bit Y-RAM (YRAM) This is a 256 x 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit address, YABx(15:0) is generated by the Address Generation Unit of the DSP core. The 24-Bit Data, YDBx(23:0), is written to and read from the Data ALU of the DSP core. The YDBx Bus is also connected to the Internal Bus Switch so that it can be routed to and from other blocks. 768 x 24-Bit Program RAM (PRAM 1280 x 24-bit for DSP1) This is a 768 x 24-Bit Single Port SRAM used for storing and executing program code. The 16-Bit PRAM Address, PABx(15:0) is generated by the Program Address Generator of the DSP core for Instruction Fetching, and by the AGU in the case of the Move Program Memory (MOVEM) Instruction. The 24-Bit PRAM Data (Program Code), PDBx(23:0), can only be written to using the MOVEM instruction. During instruction fetching the PDBx Bus is routed to the Program Decode Controller of the DSP core for instruction decoding. 256 x 24-Bit X-ROM (XROM) This is a 256 x 24-Bit factory programmed XROM. The 16-Bit address, XABx(15:0) is generated by the AGU Unit. The 24-Bit Data is multiplexed onto the XDBx Bus when the address is valid. 256 x 24-Bit Y-ROM (YROM) This is a 256 x 24-Bit factory programmed YROM. The 16-Bit address, YABx(15:0) is generated by the AGU Unit. The 24-Bit Data is multiplexed onto the YDBx Bus when the address is valid. 128 x 24-Bit Bootstrap ROM (PROM) This is a 128 x 24-Bit factory programmed Boot ROM used for storing the program sequence for initializing the DSP. Essentially this consists of a routine that is called when the M8051 requests that a DSP image be sent via the Host Interface. It is the task of the Boot code to read the data being sent by the micro from the Host Interface FIFO and store it in PRAM, XRAM, YRAM, and/or external DRAM. Operating Mode Register The operating mode register contains one bit to choose between boot mode (always from the Host Interface) or normal mode (execution from PRAM). This bit will be set when the DSP is reset (by writing to the RSDSPx bit in the CLKCNTL register). It must be cleared by the boot code to enable execution from PRAM. DSP Memory Maps The DSP memory Maps are shown in Figure 26. Serial Audio Interface (SAI) The SAI is used to deliver digital audio to the DSPs from an external source. Once processed by the DSPs, it can be returned through this interface. There is only one SAI on the chip that can be accessed by either DSP. The features of the SAI are listed below. Five Synchronized Stereo Data Transmission Lines Four Synchronized Stereo Data Reception Lines Slave operating mode, all clock lines are inputs 21/26 TDA7503 Figure 20. DSP1 and DSP0 Memory Spaces. Boot-Space P-Space $FFFF X-Space Y-Space $FFFF Boot-Space P-Space X-Space Y-Space $FFC0 X-Peripherals $FFBF $FFC0 X-Peripherals $FFBF Not Accessible Not Accessible Not Accessible Not Accessible Not Accessible Not Accessible Not Accessible Not Accessible $0500 $04FF $0300 $02FF P-RAM P-RAM $0200 $01FF $0100 $00FF $0200 $01FF $0100 $00FF X-ROM X-RAM Y-ROM Y-RAM $0040 $003F $0000 Boot-ROM X-ROM X-RAM Y-ROM Y-RAM $0040 $003F $0000 Boot-ROM DSP0 DSP1 Transmit and Receive Interrupt Logic triggers on Left/Right data pairs Receive and Transmit Data Registers have two locations to hold left and right data. Synchronous Serial Interface (SSI) The SSI is used for communication with devices with a conventional serial interface (not I2S stereo serial audio interface). The SSI shares some pins with the SAI. When the SSI is activated, some of the SAI pins are switched from the SAI to the SSI. The SAI and SSI can operate in parallel. The features of the SSI are listed below. Slave operating mode, FSYNC and SSISCK are inputs. Data sizes of 8, 16, and 24 bits are supported. Frame Sync (FSYNC) and SCK (SSISCK) signals connected to both the receiver and transmitter. Normal mode or Network mode possible. XCHG Interface (DSP to DSP Exchange Interface) The Exchange Interface peripheral provides bidirectional communication between DSP0 and DSP1. Both 24 bit word data and four bit Flag data can be exchanged. A FIFO is utilized for received data. It minimizes the number of times an Exchange Interrupt Service Routine would have to be called if multi-word blocks of data were to be received. The Transmit FIFO is in effect the Receive FIFO of the other DSP and is written directly by the transmitting DSP. The features of the XCHG are listed below. 10 Word XCHG Receive FIFO on both DSPs Four Flags for each XCHG for DSP to DSP signaling Condition flags can optionally trigger interrupts on both DSPs Host Interface(HI) The DSPs communicate with the 8051 through the Host Interface. There is a separate HI for each of the DSPs. Two Host Interfaces are included. HI0 for Host to DSP0 communication, and HI1 for Host to DSP1 communication. The 22/26 TDA7503 features of the HI are listed below. 8 Word Host Receive FIFO - DSP Side 4 Word Host Receive FIFO - Host (8051) Side Two Flags for each HI for DSP to Host signaling (can optionally trigger interrupts) Command Vector Register allows Host to trigger any DSP vectored interrupt DRAM/SRAM Interface (EMI) The External DRAM/SRAM Interface is viewed as a memory mapped peripheral. Data transfers are performed by moving data into/from data registers and the control is exercised by polling status flags in the control/status register or by servicing interrupts. An external memory write is executed by writing data into the EMI Data Write Register. An external memory read operation is executed by either writing to the offset register or reading the EMI Data Read Register, depending on the configuration. The features of the EMI are listed below. Data bus width fixed at 4 bits for DRAM and 8 bits for SRAM. Data word length choices of 16 or 24 bits. Nine DRAM address lines means 218 = 256KB addressable DRAM. Refresh rate for DRAM can be chosen among eight divider factor. SRAM relative addressing mode with multiplexed address/data lines; 214= 16KB addressable SRAM. Four SRAM Timing choices. Two Read Offset Registers. Debug Interface The Debug Port is multiplexed to both of the DSP Cores via a select pin. Only one DSP can be debugged at a time. The debug logic is contained in the core design of the DSP. The features of the Debug Port are listed below: Breakpoint Logic Trace Logic Single stepping Instruction Injection Program Disassembly CORDIC Co-Processor The CORDIC Co-Processor is used to convert rectangular to polar coordinates. . The CORDIC Unit has an 18 Bit data path throughout. When reading 24 bit words from the DSP the upper 6 bits are truncated. When writing to the DSP the upper 6 bits are zeroed. Either DSP may write an X and Y coordinate to the CORDIC unit and, 17 clock cycles later, the magnitude and angle information will be available from the CORDIC Unit. 8051 Embedded Microcontroller The microcontroller serves as the on-chip system controller and operates from 64K of external EPROM with 1K of internal RAM. In addition, it contains a small program in internal RAM that allows the micro to program the external EPROM. The micro will boot a network interface program from external EPROM. If a command to program the EPROM is received from the network then the following sequence will be initiated: The micro will read a ROM image from the network via a network chip attached to the micro's SPI. Then the micro will switch to running out of internal RAM and begin programming the external EPROM with the image read from the network. This allows the personality of the system to be set after the system has been manufactured. The external EPROM also holds the DSP programs and initializing values. The micro will copy these images to the DSP via an on-chip host interface (HI). In addition to the 8051 Core the following memory and control functions are required: Internal Memory Interface to 256 Bytes of Single Port Static RAM and 768 Bytes of AUXRAM External Memory Interface to EPROM and Memory Mapped Peripheral I/O Host Interface for Micro to DSP Communication Serial Peripheral Interface (SPI) Control Interface for Interrupts and GPIO PLL Clock Oscillator Internal Memory Interface The 8051 requires an internal memory interface to connect to the internal 256 RAM locations and the 768 Auxiliary RAM. Micro Memory Interface The 8051 core requires an external memory interface to connect to external program memory and memory mapped peripherals. This is implemented like the standard 80C51 Port 2/Port 0 Multiplexed 16 Bit Address/8 Bit Data Bus. . The signals RD, WR, XPSEN, and XALE will also be output. The External Memory Interface must also have circuitry to program the external EPROM (or any non-volatile memory) in-circuit. This means that the normal operation of the external memory interface must be altered to handle the program timing of the EPROM. By treating the Port 2/Port 0 pins as GPIO the programming can be 23/26 TDA7503 achieved in software. When this mode is entered instruction execution is switched to internal AUXRAM. Serial Peripheral Interface The 8051 core requires a serial interface to receive commands and data over the LAN. During an SPI transfer, data is transmitted and received simultaneously. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device. The SS Pin will act as a GPIO when the SPI is in master mode or the SPI is disabled. When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simultaneously shifted in a second data pin. The central element in the SPI system is the shift register and the read data buffer. The system is single buffered in the transfer direction and double buffered in the receive direction. Control Interface The 8051 requires a set of external general purpose input/output lines, two external interrupt lines, and a reset line. These signals are used by external devices to signal events to the 8051. The GPIO lines are implemented as the 8051's Port 1 GPIO. The two external interrupts are connected to the INT0 and INT1 lines on the micro. The RESET pin is used to reset the micro. PLL Clock Oscillator The PLL Clock Oscillator can accept an external clock at XTI or it can be configured to run an internal oscillator when a crystal is connected across pins XTI & XTO. There is an input divide block IDF (1 -> 32) at the XTI clock input and a multiply block MF (33 -> 128) in the PLL loop. Hence the PLL can multiply the external input clock by a ratio MF/IDF to generate the internal clock. This allows the internal clock to be within 1 MHz of any desired frequency even when XTI is much greater than 1 MHz. It is recommended that the input clock is not divided down to less than 1 MHz as this reduces the Phase Detector's update rate. The clocks to the DSP and the 8051 can be selected to be either the VCO output divided by 2 or 4 respectively, or be driven by the XTI pin directly. The crystal oscillator and the PLL will be gated off when entering the power-down mode (by setting bit 1 of the PCON Register). M8051 Interrupts The M8051 Core provides for 5 interrupt sources, INT1, INT0, TIMER1, TIMER0, and SERIAL Data. There exists a corresponding Interrupt Enable register and Interrupt Priority Register. 24/26 TDA7503 DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.17 0.09 mm TYP. MAX. 1.60 0.15 1.40 0.22 1.45 0.27 0.20 16.00 14.00 12.00 0.50 16.00 14.00 12.00 0.60 1.00 0.75 0.018 0.002 0.053 0.007 0.003 MIN. inch TYP. MAX. 0.063 0.006 0.055 0.009 0.057 0.011 0.008 0.630 0.551 0.472 0.019 0.630 0.551 0.472 0.024 0.0393 3.5(min.), 7(max.) 0.030 OUTLINE AND MECHANICAL DATA TQFP100 D D1 D3 A A2 A1 75 76 51 50 0.076mm .003 inch Seating Plane e E3 E1 E B PIN 1 IDENTIFICATION 100 1 25 26 K TQFP100M C L L1 25/26 TDA7503 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 26/26 |
Price & Availability of TDA7503
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |